Accurate timing for a system is provided by clocks. To fulfill the need to send multiple clock signals to the various circuit elements in a system, clock distribution chips are provided. Such chips are capable of distributing a clock signal across a printed circuit board of a system or among several printed circuit boards. Typical clock distribution chips include at least one clock input terminal for receiving an external "reference" clock signal. Alternatively, some or all of the clock signals may be generated by the chip itself. Typically, the received or generated clock signal is then split into multiple clock signals on separate signal paths for receipt by the chip's several clock drivers. The drivers distribute these multiple clock signals as outputs through multiple clock output terminals. The clock signals then propagate over wire traces across the printed circuit board to the recipient circuit elements or chips in the system.
Clock distribution chips are used especially in high speed systems, where accurate timing is essential to avoid conflicts on system busses that are used by several circuit elements of these systems, and also to minimize as much as possible various circuit elements having to wait unduly long time periods for other circuit elements to complete their operations before beginning the next operation in a sequence of successive program instructions. As systems get faster, and hence use shorter clock cycles, "relativistic" effects become important. Note that the time at any particular location in the system, such as at a circuit element or chip of the system, is observed as a phase of a clock signal received at that location. Because of different clock delays, the time observed at one location in the system may not be the same as the time observed at another location. The relative offset in the observed time or clock phase at different locations in the system due to clock delays is called "clock skew". As clock speeds become greater than 50 MHz, the corresponding clock cycle or period becomes less than 20 ns, and any clock skew becomes a significant portion of this clock period.
Clock delays are caused by several factors. First, it takes time for a clock signal to travel down a wire trace or other signal path to its destination, because the propagation speed is finite. A propagation delay of one nanosecond for every 15 to 18 centimeters of unloaded wire trace is typical. Skew can result if the wire trace lengths to the various circuit elements differ substantially from one another. To minimize this skew, system designers typically place the clock chip in a central location that minimizes as much as possible the variation in the propagation distances from the clock distribution chip to the receiving circuit elements in the system. Second, clock delays may be caused by the fanout on the clock distribution chip from a single received or generated reference clock signal to multiple clock signal outputs. Typical fanout delays are 2 nanoseconds for a fanout of four, doubling to 4 nanoseconds for a fanout of eight. If multiple clock distribution chips are needed, all should have the same fanout to avoid skew from this source of clock delay. Skew can also result if the multiple clock drivers on the clock distribution chip are not exactly matched. Due to manufacturing tolerances there is an intrinsic pin-to-pin skew among the chip's different clock outputs of about 0.5 to 1.0 nanoseconds for identical loads. Third, clock delays are caused by the loads on each of the clock signal paths. The clock drivers take different amounts of time to charge up the different RC loads on the various signal paths. The speed of propagation of a signal across a board tpd'=tpd .sqroot.1+(C.sub.d /C.sub.o), where tpd is the signal delay per unit length for an unloaded trace, C.sub.d is the distributed capacitance of the load (typically about 0.8-1.6 pF/cm), and C.sub.o is the intrinsic capacitance of the trace (typically about 0.8 pF/cm). The load will typically increase the clock delay by anywhere from 40% to 70% over the delay on an unloaded trace. Significant clock skew will result if the loads provided by the recipient circuit elements are not substantially identical. Typically, a circuit designer will use clock distribution chips with low intrinsic inter-driver skew and try to equalize the loads on the various signal paths. Skew can also result from different input threshold levels of the input buffers of the various recipient circuit elements or chips, because of the finite rise time of the clock signal. For example, the difference between a 1.5 V threshold for a TTL chip and a 2.5 V for a CMOS chip can cause a 1 ns clock skew between these two circuit types.
After taking all of these factors into account, the typical clock skew T.sub.skew in a well designed system is about 2 or 3 nanoseconds. This is dead time and forces the designer to design the system to tolerances of T.sub.period -T.sub.skew, where T.sub.period is period of the clock signal. In a 50 MHz system with a 20 ns clock period, a 3 ns skew means that 15% of the clock cycle is wasted. In faster systems, an even greater portion of the clock cycle will be wasted meeting system tolerance requirements due to the skew. Depending on the nature of the particular system, a one nanosecond clock skew may be intolerable, even at 50 MHz speeds.
It is known to use phase-locked-loop-like techniques and a reference clock to dynamically adjust the delays on other non-clock signal paths. In U.S. Pat. No. 4,899,071, Morales describes an active digital delay line circuit having two or more arrays of series-connected voltage-controlled delay elements. A reference clock and a delayed reference clock, formed by passing the reference clock through one of the arrays, are compared by a phase detector, which outputs a control voltage representation of the signal delay. This control voltage is applied to control inputs of the delay elements in each array. Thus, Morales uses a phase-locked loop to correlate on-silicon delays with the reference clock period, and then uses that result to generate or produce desired time delays of input signals received by the delay circuit.
It is an object of the invention to provide a clock distribution chip that results in reduced clock skew in systems using this chip.